`timescale 1ns / 1ps

module test;

    reg[31:0] op1;
    reg[31:0] op2;
    reg cin;
    
    wire[31:0] result;
    wire cout;

    adder adder_module(
        .op1(op1),
        .op2(op2),
        .cin(cin),
        .result(result),
        .cout(cout)
    );
    
    initial begin
        op1 = 0;
        op2 = 0;
        cin = 0;
        #100;
    end
        always #10 op1 = 15;
        always #10 op2 = 12;
        always #10 cin = 0 % 2;

endmodule
